SNUG Proceedings

Sort and filter by Location, Year, or Content Type to locate the papers, presentations, and session recordings that are applicable to you. You can also search all SNUG event proceedings using the keyword search below.

2017 - Taiwan

Achieve Timing Closure Faster in 8M Large Flatten Design with IC Compiler II CCD Flow

Ted Hong - Vatics

Track - Backend Design

2017 - Taiwan

Advanced Process Implementation Experience Sharing – From Synthesis to Tapeout

TK Tsai - MediaTek

Track - Backend Design

2017 - Taiwan

Best Practices for High-Performance, Energy Efficient Implementations of the Latest ARM® Processors in 16-nanometer FinFET Compact (16FFC) Process Technology Using Synopsys Galaxy™ Design Platform

JC Yu - Arm; Joe Walston - Synopsys

Track - Backend Design

2017 - Taiwan

Boost Productivity, Design Performance, Power and Area with IC Compiler II - Complex Congestion and Performance-Driven with Hi-End DTV Design (Best Paper Winner - Backend Design)

JR Chuang - MStar

Track - Backend Design

2017 - Taiwan

IC Compiler II Migration with Improved QOR/TTR

林志鴻 Chih-Hung Lin - Nuvoton

Track - Backend Design

2017 - Taiwan

IC Compiler II Release Update

Dave Tsai - Synopsys

Track - Backend Design

2017 - Taiwan

IC Compiler II: Faster Runtime and Improved QOR

JC Yu - Arm

Track - Backend Design

2017 - Taiwan

Multi-Million Gates GPU Block Implementation in Flatten Flow with IC Compiler II (Best Paper Winner - Backend Design)

Cloud Tsai - Realtek

Track - Backend Design

2017 - Taiwan

Routability Improvement Using ICC2 RM+ on a 6M-inst 28nm Design

Evan Chou - Novatek

Track - Backend Design

2017 - Taiwan

The Automatic Generation of FMEDA of ISO26262 for IP Design with Lynx Assistant

Jeff Yang - ITRI

Track - Backend Design