SNUG Proceedings

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2018 - Penang

A Holistic Methodology of Zero-cycle Timing Path for Latency Reduction (Best Paper - Implementation I)

Simin Xu, Khai Sean Yeoh - Xilinx

Track - Implementation I

2018 - Penang

A Novel Approach in Security Implementation and Clock Tree Synthesis using IC Compiler II

Samuel Jigme Harrison, Lay Hong Tan - STMicroelectronics

Track - Implementation I

2018 - Penang

Achieve Faster Design Closure Utilizing IC Compiler II Placement and Optimization Technologies

Anusha Reddy Sindhwala - Synopsys

Track - Implementation I

2018 - Penang

Achieving Best QOR and Fastest Time to Results with Synopsys' Fusion Platform

Arvind Narayanan - Synopsys

Track - Implementation I

2018 - Penang

CCD Technology Highlight/Customer (Renesas) Success Experience Sharing

Anusha Reddy Sindhwala - Synopsys; Le Ngoc Vu Phuoc - Renesas

Track - Implementation I

2018 - Penang

High Performance Design Optimization Technique Via Guided Useful Skew

Track - Implementation I

2018 - Penang

IC Compiler II Technology Update

Arvind Narayanan - Synopsys

Track - Implementation I

2018 - Penang

A Systematic and Accurate Methodology for Complex Programmable Logic Interconnect Performance (Best Paper - Implementation II)

Track - Implementation II

2018 - Penang

Best Practices in Synthesis Area Recovery Using optimize_netlist

Lou Chin Leong - Chipglobe; Kim Wee, NG - Infineon

Track - Implementation II

2018 - Penang

Design Compiler Recent Technology Enhancements, QoR Improvements & Roadmap/Customer Success Experience Sharing

Hari Narayan Shanmugam - Synopsys

Track - Implementation II