SNUG Proceedings

Sort and filter by Location, Year, or Content Type to locate the papers, presentations, and session recordings that are applicable to you. You can also search all SNUG event proceedings using the keyword search below.

2018 - Silicon Valley

First Pass Silicon Success Using Custom Compiler

Varun Ramaswamy - Seagate

Track - Custom Implementation & AMS

2018 - Silicon Valley

HSPICE, FineSim, Custom WaveView Updates and a Tutorial on SPICE Acceleration for Analog Circuits Using FineSim SPICE

Gim Tan - Synopsys

Track - Custom Implementation & AMS

2018 - Silicon Valley

Physically-Aware Simulation and Electrical Analysis During Layout

Sandrine Rothblez, Denis Goinard, Dave Reed - Synopsys

Track - Custom Implementation & AMS

2018 - Silicon Valley

Vector Independent Timing Verification for Full Custom Memories Using Verilog-A and CustomSim

Ramasamy Adaikkalavan, Ben Bowers - Qualcomm

Track - Custom Implementation & AMS

2018 - Silicon Valley

Bringing Digital Intelligence to the Design Platform

Stelios Diamantidis, Joe Walston - Synopsys

Track - Machine Learning

2018 - Silicon Valley

Data Driven Approaches to Improving Simulation Methodologies in Synopsys Mixed-Signal Ips

Mohan Mohan, Brian LaRochelle, Marco Oliveira, Dinesh Garg, Yevgeni Sevinyan, Bob Lefferts - Synopsys

Track - Machine Learning

2018 - Silicon Valley

Full Chip FinFET Self-Heat Prediction Using Machine Learning (3rd Place Best Paper)

Chintan Shah, Yi Du, Chi Keung Lee, Miloni Mehta, Kirk Twardowski - NVIDIA

Track - Machine Learning

2018 - Silicon Valley

22FDx IC Compiler II Body-Bias Interpolation and Correlation to PrimeTime

Haritez Narisetty, Ramya Srinivasan - GLOBALFOUNDRIES

Track - Physical Implementation

2018 - Silicon Valley

Best Practices for High-Performance, Energy Efficient Implementations of the Latest Arm® Processors in 7-nanometer FinFET (7FF) Process Technology Using Synopsys Design Platform

Deep Kanwar Singh Bhullar - Arm; Joe Walston, Michael Montana - Synopsys

Track - Physical Implementation

2018 - Silicon Valley

Block Level Floorplan Debug with IC Compiler II

Pete Churchill - Synopsys

Track - Physical Implementation