SNUG Proceedings

Sort and filter by Location, Year, or Content Type to locate the papers, presentations, and session recordings that are applicable to you. You can also search all SNUG event proceedings using the keyword search below.

2018 - Europe

Sensitivity Study of the Parasitics of Advanced FinFETs

Pieter Schuddinck, Dmitry Yakimets, Bertrand Parvais, Anda Mocuta - imec; Ralph Iverson, Senthil Annamalai, Krishnakumar Sundaresan - Synopsys

Track - Advanced Nodes

2018 - Europe

A Simulation-Based Failure Rate Analysis for Automotive Applications Using CustomSim

Radu H Iacob, Wei Cong - Kilopass Technology, Inc.

Track - Analog / Mixed-Signal

2018 - Europe

Custom MOSRA Model with Gate Voltage Effect for Aging Simulation

Heidrun Alius, Thomas Gneiting - AdMOS GmbH; Kerwin Khu, Jochen Werno, Reinhard Erwe, Maria-Cristina Vecchi - TDK-Micronas GmbH

Track - Analog / Mixed-Signal

2018 - Europe

Unlocking the Power of SV in a Mixed Signal Simulation with Verilog-A

Peter Grove - Dialog Semiconductor; Andrew Milne - Synopsys

Track - Analog / Mixed-Signal

2018 - Europe

Custom WaveView Updates and a Tutorial on Design Debugging Using DesignView

Michael Yang, Manu Velayudhan Pillai - Synopsys

Track - Analog Mixed-Signal / Debugging

2018 - Europe

Examining the Latest VCS AMS and Verdi AMS Features for Enhanced Usability and Debug During Mixed Signal Simulation and Verification

Peter Thompson - Synopsys

Track - Analog Mixed-Signal / Debugging

2018 - Europe

Best Practices for High-Performance, Energy Efficient Implementations of the Latest Arm Processors in 7-nanometer FinFET (7FF) Process Technology Using Synopsys Design Platform

Phil Morris - Arm; Alan Gibbons - Synopsys

Track - Arm IP

2018 - Europe

22FDx Low Voltage Design Deploying Dynamic Body Bias and Liberty Variation Format (Technical Committee Award)

Chenbo Liu, Haritez Narisetty, Ramya Srinivasan, Siddharth Sawant, Ulrich Hensel - GLOBALFOUNDRIES

Track - Automotive

2018 - Europe

An Automated Behavioral Model Generation and Schematic Comparison Tool for Analog Circuits in SoC Validation (3rd Place Best Paper)

Track - Automotive

2018 - Europe

Enabling Fault Injection in an Automotive VP using Simulation Probes

Aditya Raghunath, Dineshkumar Selvaraj, Sandeep Puttappa, Jens Harnisch - Infineon Technologies

Track - Automotive