SNUG Proceedings

Sort and filter by Location, Year, or Content Type to locate the papers, presentations, and session recordings that are applicable to you. You can also search all SNUG event proceedings using the keyword search below.

2017 - Austin

Cell-Aware Test for Lower DPPM and Faster Silicon Yield Ramp with Diagnostics

Brian Archer, Steve Palosh – Synopsys

Track - Test

2017 - Austin

Meet Your Test Quality and Cost Goals with Unprecedented Speed

Brad MacMonagle – Synopsys

Track - Test

2017 - Austin

Pattern Translation and Verification of DFTMAX Ultra Patterns in Hierarchical ATPG

Hui Liu, Neil Hao, Vincent Wang – Advanced Micro Devices

Track - Test

2017 - Austin

Scoring Big Points (Coverage, Cost, QoR) With Test Points. A DFT Hat Trick!

Don Dattani, Raj Shah – Cognitive Systems; Don Skinner – Synopsys

Track - Test

2017 - Austin

SpyGlass® DFT ADV: High Testability, SoC Connectivity, Functional Safety and Reliability

Al Joseph – Synopsys

Track - Test

2017 - Austin

A Unique Approach for SoC Reset Connectivity Verification

Ratika Goyal, Amol Bhinge – NXP Semiconductors; Jiri Prevratil – Synopsys

Track - Verification Continuum I

2017 - Austin

Are you Planning to Fail or Failing to Plan?

Aditya Musunuri, Amol Bhinge – NXP Semiconductors; Taruna Reddy – Synopsys

Track - Verification Continuum I

2017 - Austin

Boosting Debug Productivity - Practical Applications of Verdi Debug Innovations

Alex Wakefield – Synopsys

Track - Verification Continuum I

2017 - Austin

Fast and Furious: A 8x Runtime Performance

Sujit Shah – Centaur Technology, Wei-Hua Han – Synopsys

Track - Verification Continuum I

2017 - Austin

Formal Verification of a Pipelined Multiplier Design for a High Performance Processor Core

Pratyush Jain, Kurt Olin – Advanced Micro Devices; Yong Liu – Synopsys

Track - Verification Continuum I