SNUG Proceedings

Sort and filter by Location, Year, or Content Type to locate the papers, presentations, and session recordings that are applicable to you. You can also search all SNUG event proceedings using the keyword search below.

2018 - Boston

Architectural Formal Verification: A 3-Step Guide

Kamal Sekhon, Roger Sabbagh - Oski Technology

Track - Verification Continuum

2018 - Boston

Auditing the UVM Resource Database (Technical Committee Best Paper Award)

Fitzgerald Huang, Jack Perveiler, Nitin Prakash, Rohit Thakar - Cavium

Track - Verification Continuum

2018 - Boston

Improving Simulation Throughput with Fine-Grained Parallelism (FGP)

June Wang - Acacia Communications; Joseph Basmaji - Synopsys

Track - Verification Continuum

2018 - Boston

Stimulus Driven Methodology for Emulation Based Software and Hardware Verification of AMD x86 Microprocessor Designs

Oleg Petlin, Adithya Yalavarti - Advanced Micro Devices; John Zaghi - Synopsys

Track - Verification Continuum

2018 - Boston

TCP/IP Socket Based Communication for SystemVerilog Simulation

Victor Besyakov - BTA Design Services

Track - Verification Continuum

2018 - Boston

Using (auto-generated) SystemVerilog Constraints to Test (auto-generated) C Models

Henry Cox, John Chang - Mediatek

Track - Verification Continuum

2018 - Boston

Wait Management in UVM 1.2 RAL: Cutting Sequence Delay the No-Wait Way (Best Presentation - Second Place)

Steven K. Sherman - Advanced Micro Devices

Track - Verification Continuum

2018 - Europe

Custom Compiler Template-Based Design for Layout Automation

Damian Roberts - Synopsys

Track - Advanced Layout Methods

2018 - Europe

IC Validator - Physical Signoff Challenges for All Edges

Christen Decoin, David DeMarcos - Synopsys

Track - Advanced Layout Methods

2018 - Europe

DTCO Flow for Device Exploration

Dmitry Yakimets, Pieter Schuddinck, Philippe Matagne, Bertrand Parvais, Anda Mocuta - imec

Track - Advanced Nodes