SNUG Proceedings

Sort and filter by Location, Year, or Content Type to locate the papers, presentations, and session recordings that are applicable to you. You can also search all SNUG event proceedings using the keyword search below.

2013 - Canada

Verifying Crossover Signals in Low Power Simulation

Ashwini Holla, Andy Ray, Shu-Shia Chow - Advanced Micro Devices, Inc.

Track - Verification

2013 - France

IC Compiler Custom Co-Design Workshop

Synopsys

Track - AMS Co-Design

2013 - France

"Digital Supplies are Analog !" - CustomSim-VCS with UPF

Pierre-Yves Alla - Synopsys

Track - AMS Design and Verification

2013 - France

Aging Model Implementation using MOSRA API Flow from HSPICE to CustomSim (XA) FastSPICE: Applications at STMicroelectronics

Florian Cacho, Vincent Huard - STMicroelectronics, Patrice Loth, Manjunatha Vadiarillat, Zhaoping Chen, Joddy Wang - Synopsys

Track - AMS Design and Verification

2013 - France

An Accurate Path Verification to Secure and to Speed Up Nanometer Design Closure

Salvatore Santapà, Alessandro Valerio, Pierluigi Daglio (STMicroelectronics), Andrea Barletta - Politecnico of Milan , Massimo Prando - Synopsys

Track - AMS Design and Verification

2013 - France

Circuit Check Extension to Optimize ERC Flow, User Experience, Guidelines for Expert and Novice Users

Alessandro Valerio, Salvatore Santapà, Pierluigi Daglio - STMicroelectronics, Carlo Borromeo, Chi-Tzung Wang - Synopsys

Track - AMS Design and Verification

2013 - France

Full Front-to-Back Custom Design Flow: “The Power of Custom Designer-SE & Laker" (The tutorial is followed by a Customer Testimonial)

Guillaume Thomas, - Synopsys, Alain Vigne - BlinkSight

Track - AMS Design and Verification

2013 - France

Improve IC-Level Verification Coverage by using Assertions with CustomSim-VCS Multi-Thread Real Number Flow

François Ravatin, Sébastien Cliquennois - ST-Ericsson, Philippe Brahic - Synopsys

Track - AMS Design and Verification

2013 - France

The Art of Reliability: Guidelines to Reduce IR-drop and Electro-Migration Effects in Full Custom Designs

Paolo Valente, Alessandro Valerio - STMicroelectronics, Claudio Rallo - Synopsys

Track - AMS Design and Verification

2013 - France

Delay Faults Detection in Synchronous Clock Domain Logic

Ravindra Babu Nayudu - Abilis Systems, Frank Nolting - Synopsys

Track - Design for Test and Yield Analysis