SNUG Proceedings

Sort and filter by Location, Year, or Content Type to locate the papers, presentations, and session recordings that are applicable to you. You can also search all SNUG event proceedings using the keyword search below.

2013 - India

WB3.1 User Paper: The Last Microwatt - Challenges in Pre Silicon Power Estimation for Low-Power SoCs

Track - IC Design - Signoff

2013 - India

WB3.2 User Paper: Method for Collapsing Multiple Modes Timing Constraints (Outstanding Technical Paper Award)

Rajkumar Agrawal, Vivek Manikandan LSI India Research & Development Pvt Ltd

Track - IC Design - Signoff

2013 - India

WB3.3 Tutorial: Mode Merging using PrimeTime-GCA

Synopsys

Track - IC Design - Signoff

2013 - India

WD1.1 User Paper: Increase ATPG Throughput While Reducing Care Bits: Optimizing Transition Fault Patterns (Outstanding Technical Paper Award)

Mudasir Kawoosa, Rajesh Mittal, Prakash Narayanan - Texas Instruments, Surya Samavedam - NVIDIA

Track - IC Design - Test and FPGA

2013 - India

WD1.2 User Paper: Effective ATPG with Hierarchical DFT Methodology for SoC

Seema Shareef, Soham Roy, Ashwini Shankar - Wipro Technologies

Track - IC Design - Test and FPGA

2013 - India

WD1.3 User Paper: Sharing Scan-Ins For Similar Cores

Deepak Agrawal, Daryl Pereira, Sanjay Shinde, Aanand Venkatachalam - LSI India

Track - IC Design - Test and FPGA

2013 - India

WD1.4: New, Innovative Test Technology to Reduce the Cost of Quality

Rohit Kapur - Synopsys

Track - IC Design - Test and FPGA

2013 - India

TB1.1 Tutorial: Addressing Low Power Verification Challenges with VCS

Synopsys

Track - IC Verification

2013 - India

TB1.2 Tutorial: Transaction Level Verification with Zebu Server

Synopsys

Track - IC Verification

2013 - India

TB2.1 Tutorial: Advanced Verification Debug Productivity with Verdi3 and Siloti

Synopsys

Track - IC Verification