SNUG Proceedings

Sort and filter by Location, Year, or Content Type to locate the papers, presentations, and session recordings that are applicable to you. You can also search all SNUG event proceedings using the keyword search below.

2019 - Austin

Physical Verification on the Cloud - Solving Physical Signoff TAT Challenges

Jonathan White - Synopsys

Track - Cloud

2019 - Austin

Scaling Verification Workloads on the Cloud

Jyotsna Repaka- Google, Melvin Cardozo - Synopsys

Track - Cloud

2019 - Austin

Analog Design Closure with Custom Compiler

Soni Kapoor - Synopsys

Track - Custom Implementation and AMS

2019 - Austin

Chip-Level IDDQ Current Simulation and Leaky Path Detection using CustomSim

Krishna Madabhushi, Jianjun Liu, Venkatesh Kurahatti, Sudip Dandnaik, Scott Haskin - Medtronic; Joseph Perttu - Synopsys

Track - Custom Implementation and AMS

2019 - Austin

Chip-Level Verification of an RF ASIC with CustomSim/VCS

Greg Tumbush - EM Microelectronic

Track - Custom Implementation and AMS

2019 - Austin

Bottom-Up Timing Constraints Integration

Joseph Yang - Xilinx

Track - Frontend Implementation

2019 - Austin

Design Compiler® NXT – Latest Advances

Jason Perez - NXP Semiconductors, Danny Bradley - Synopsys

Track - Frontend Implementation

2019 - Austin

Formality Interactive and Automatic ECO Solutions

Steve Lamb - Synopsys

Track - Frontend Implementation

2019 - Austin

Graphic Core IP Power Optimization Using minPower Guided and SAIF Driven Synthesis

Chris Meng, Zhiwei Tang - Advanced Micro Devices

Track - Frontend Implementation

2019 - Austin

Latest Advances in PrimeTime-ADVPlus to Address Design Closure at 5nm and Below

Troy Epperly - Synopsys

Track - Frontend Implementation